1. Field of the Invention
The present invention relates to a midpoint potential generating circuit for use in a semiconductor device.
2. Description of the Related Art
In a semiconductor device such as a DRAM (random access memory), a decoupling capacitor is generally disposed between a power wire and a grounding wire in order to suppress a fluctuation of a supply voltage. There has been proposed that the decoupling capacitor is formed of a stack capacitor used in a memory cell of the DRAM.
For example, JP 10-12838A discloses that a plurality of memory cell capacitors are separately disposed to realize an etendue efficient capacity element.
On the other hand, Japanese Patent 3399519 discloses a bias circuit that supplies a bias voltage to a power supply circuit having an array capacitor with a low voltage limit connected in series as a DRAM power supply.
Meanwhile, in the power supply circuit having the stack capacitors connected in series to realize a large capacity, a circuit that provides a constant midpoint potential to nodes of the capacitors is provided in order that a voltage that is applied to the capacitors does not exceed a limit value.
FIG. 1 is a circuit diagram showing a conventional power supply circuit for a semiconductor device. In FIG. 1, a booster power supply circuit 11 boosts a voltage VDD and generates a supply voltage VPP that is supplied to an internal circuit 12.
Capacitors C1 and C2 are connected in series, the supply voltage VPP is applied to an upper terminal of the capacitor C1, a bias voltage Vbias is applied to a node between the capacitor C1 and the capacitor C2, and a lower terminal of the capacitor C2 is grounded.
An n-channel MOS transistor TR1 and a p-channel MOS transistor TR2 are connected tandem, and a voltage at a node between those transistors TR1 and TR2 is applied to the node of the capacitors C1 and C2 as the bias voltage Vbias.
To a gate of the MOS transistor TR1 is applied a voltage Vrefl developed at a node between resistors R11 and R12 among the resistors R10, R11 and R12 which are connected in series. To a gate of the MOS transistor TR2 is applied a voltage Vrefh developed at a node between the resistors R10 and R11.
Accordingly, when a voltage resulting from adding a threshold voltage Vth of the MOS transistor TR1 to the bias voltage Vbias is lower than a lower limit Vrefl of a voltage that is determined according to the supply voltage VPP outputted from the booster power supply circuit 11 and a resistance ratio of a series resistor consisting of the resistor R10 and the resistor R11 to the resistor R12, the MOS transistor TR1 turns on to charge the capacitor C2.
On the other hand, when a voltage resulting from adding the threshold value Vth of the MOS transistor TR2 to the bias voltage Vbias is higher than an upper limit Vrefh of a voltage that is determined according to a resistance ratio of the resistor R10 to a series resistor consisting of the resistors R11 and R12, the MOS transistor TR2 turns on to discharge the capacitor C2.
The above operation is repeated so that the midpoint potential of the capacitors C1 and C2 is controlled in a range between the upper limit and the lower limit.
FIG. 2 is a circuit that compares the upper limit Vrefh and the lower limit Vrefl of the voltage with the bias voltage Vbias by means of comparators CP1 and CP2 disposed upstream of the MOS transistors TR3 and TR4. In the following description, the same parts as those in FIG. 1 are designated by like references, and their description will be omitted.
In FIG. 2, MOS transistors are connected tandem between the power supply VDD and the ground in such a manner that a p-channel MOS transistor TR3 is disposed at an upper position and an n-channel MOS transistor TR4 is disposed at a lower position.
The lower limit Vrefl of the voltage is inputted to an inverting input terminal of the comparator CP1, and the upper limit Vrefh of the voltage is inputted to an inverting input terminal of the capacitor CP2.
Noninverting input terminals of the comparators CP1 and CP2 are inputted with a voltage obtained by dividing the bias voltage Vbias by resistors R20 and R21.
The operation of this circuit is basically identical with the circuit shown in FIG. 1, and the bias voltage Vbias is controlled in such a manner that the voltage divided by the resistors R20 and R21 falls within a range between the upper limit and the lower limit.
In this example, the operation of starting the midpoint potential generating circuit shown in FIG. 1 will be described with reference to FIG. 3. Normally, the resistors R10, R11 and R12 to be used are large in resistance in order to reduce the power consumption during stationary operation. For that reason, the time constant becomes large, and a given period of time is required until the voltages Vrefh and Vrefl determined according to the divided ratio of the resistors R10, R11, and R12 reach design values at the rising time of the supply voltage.
Under the above circumstances, since the gradient of a potential rising curve of the capacitor C2 is higher than the gradients of the rising curves of the voltages Vrefh and Vrefl (period T1) as shown in FIG. 3, the bias voltage Vbias that is a midpoint potential between the capacitors C1 and C2 may be higher than the upper limit Vrefh of the voltage.
When the bias voltage Vbias becomes higher than the upper limit Vrefh, charges in the capacitor C2 are discharged under the control, and the bias voltage Vbias is decreased (period T2).
Thereafter, when the bias voltage Vbias becomes lower than the lower limit Vrefh, the capacitor C2 restarts to be charged.
As described above, because the capacitor C2 is discharged at the rising time of the supply voltage, there arises such a problem that a time is required until the midpoint potential between the capacitors C1 and C2 reaches a desired voltage.
In addition, in the case where the bias voltage Vbias is decreased after the supply voltage VPP has reached a desired value VPPtarget, the booster power supply circuit 11 charges the capacitor C1 so as to rise in the potential of the capacitor C1. Thereafter, when the bias voltage Vbias rises until the midpoint potential between the capacitors C1 and C2 rises, a voltage across the capacitor C2 becomes higher than a normal voltage. As a result, the voltage VPP across the capacitors C1 and C2 is caused to be higher than the desired voltage VPPtarget (period T4).
In the power supply circuit having a high-capacity capacitor, since a leak current is suppressed, the supply voltage VPP is not immediately decreased.
Since the supply voltage VPP across the capacitors C1 and C2 is applied to an internal circuit of the semiconductor device, the reliability of the internal circuit in the semiconductor device is affected by the supply voltage VPP being too higher than the desired value.
In addition, in the conventional circuit shown in FIGS. 1 and 2, since the booster power supply circuit 11 operates from the starting time, the current consumption increases because the boosting operation is conducted from a state where the supply voltage VDD is low. Accordingly, in the case where the booster power supply circuit 11 is used in a device such as a portable terminal device which is driven by a battery, there arises such a problem that the battery voltage decreases, to thereby make the operation of the system defective.